The present invention relates generally to clock and data recovery circuits and, more particularly, to clock and data recovery circuits operable without an external reference clock.
Some communication systems transmit data serially over a channel such as a fiber optic cable. A transmitter in a serial communication system transmits data in a data signal with clocking information signaled implicitly by the timing of transitions in the data signal. A receiver recovers both the transmitted data and a corresponding clock signal. Circuitry in the receiver performing such operations is often termed a clock and data recovery circuit or more commonly a CDR. The clock and data recovery circuit commonly includes voltage-controlled oscillators, phase detectors, charge pumps, filters, and other circuitry of an analog or quasi-analog nature.
Many clock and data recovery circuits operate using a reference clock signal, for example, to aid in clock recovery by having a reference clock signal with a frequency close to some sub-multiple of the data rate. The reference clock signal may be used to tune or reduce an operating frequency range of circuitry in the clock and data recovery circuit. The reference clock signal often comes from a reference clock in the form of a crystal oscillator or similar precision source. Provisioning of the reference clock may be expensive, occupy a large space, or have other undesirable impacts.
In some applications, serial data may be received at different data rates with the receiver operating at corresponding different frequencies. In such applications, a CDR may be provided with multiple reference clock signals, one for each data rate, sourced from multiple reference clocks. This may substantially increase the expense of or space required for clock and data recovery circuits using external reference clock signals.